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| cy14b101ka/cy14b101ma 1 mbit (128k x 8/64k x 16) nvsram with real time clock cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document #: 001-42880 rev. *d revised august 28, 2009 features 1 mbit nvsram ? 25 ns and 45 ns access times ? internally organized as 128k x 8 (cy14b101ka) or 64k x 16 (cy14b101ma) ? hands off automatic store on power down with only a small capacitor ? store to quantumtrap nonvolatile elements is initiated by software, hardware, or autostore on power down ? recall to sram initiated on power up or by software high reliability ? infinite read, writ e, and recall cycles ? 200,000 store cycles to quantumtrap ? 20 year data retention real time clock ? full featured real time clock ? watchdog timer ? clock alarm with programmable interrupts ? capacitor or battery backup for rtc ? backup current of 350 na (typ) industry standard configurations ? single 3v +20%, ?10% operation ? industrial temperature ? 44-pin and 54-pin tsop ii and 48-pin ssop packages ? pb-free and rohs compliance functional description the cypress cy14b101ka/cy14b101ma combines a 1 mbit nonvolatile static ram with a full featured real time clock in a monolithic integrated circ uit. the embedded nonvolatile elements incorporate quantumtrap technology producing the world?s most reliable nonvolatile memory. the sram is read and written an infinite number of times, while independent nonvolatile data resides in the nonvolatile elements. the real time clock function provides an accurate clock with leap year tracking and a programmable, high accuracy oscillator. the alarm function is programmable for periodic minutes, hours, days, or months alarms. there is also a programmable watchdog timer for process control. static ram array 1024 x 1024 r o w d e c o d e r column i/o column dec i n p u t b u f f e r s power control store/recall control quatrum trap 1024 x 1024 store recall v cc v ca p hsb a 0 a 1 a 2 a 3 a 4 a 10 a 11 software detect a 14 -a 2 oe ce we bhe ble a 5 a 6 a 7 a 8 a 9 a 12 a 13 a 14 a 15 a 16 dq 0 dq 1 dq 2 dq 3 dq 4 dq 5 dq 6 dq 7 dq 8 dq 9 dq 10 dq 11 dq 12 dq 13 dq 14 dq 15 rtc mux a 16 -a 0 x out x in int v rtcbat v rtccap logic block diagram [1, 2, 3] notes 1. address a 0 - a 16 for x8 configuration and address a 0 - a 15 for x16 configuration. 2. data dq 0 - dq 7 for x8 configuration and data dq 0 - dq 15 for x16 configuration. 3. bhe and ble are applicable for x16 configuration only. [+] feedback
cy14b101ka/cy14b101ma document #: 001-42880 rev. *d page 2 of 30 pinouts figure 1. pin diagram - 44-pin, 54-pin tsop ii, and 48-pin ssop pin definitions pin name i/o type description a 0 ? a 16 input address inputs used to select one of the 131,072 bytes of the nvsram for x8 configuration. a 0 ? a 15 address inputs used to select one of the 65,536 words of the nvsram for x16 configuration. dq 0 ? dq 7 input/output bidirectional data i/o lines for x8 configuration . used as input or output lines depending on operation. d q 0 ? dq 15 bidirectional data i/o lines for x16 configuration . used as input or output lines depending on operation. nc no connect no connects . this pin is not connected to the die. we input write enable input, active low . when the chip is enabled and we is low, data on the i/o pins is written to the specific address location. ce input chip enable input, active low . when low, selects the chip. when high, deselects the chip. oe input output enable, active low . the active low oe input enables the data output buffers during read cycles. deasserting oe high causes the i/o pins to tristate. bhe input byte high enable, active low. controls dq15 - dq8. ble input byte low enable, active low . controls dq7 - dq0. x out output crystal connection. drives crystal on start up. x in input crystal connection . for 32.768 khz crystal. v rtccap power supply capacitor supplied backup rtc supply voltage . left unconnected if v rtcbat is used. v rtcbat power supply battery supplied backup rtc supply voltage . left unconnected if v rtccap is used. nc a 8 xin xout v ss dq 6 dq5 dq4 v cc a 13 dq 3 a 12 dq 2 dq 1 dq 0 oe a 9 ce nc a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 11 a 7 a 14 a 15 a 16 nc nc nc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 44 - tsop ii a 10 v rtcbat we dq 7 hsb int v ss v cc v cap v rtccap (x8) nc dq 7 dq 6 dq 5 dq 4 v cc dq 3 dq 2 dq 1 dq 0 nc a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 7 v cap we a 8 a 10 a 11 a 12 a 13 a 14 a 15 nc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 54 - tsop ii oe ce v cc int v ss nc a 9 nc nc 54 53 52 51 49 50 hsb bhe ble dq 15 dq 14 dq 13 dq 12 v ss dq 11 dq 10 dq 9 dq 8 (x16) v rtccap v rtcbat xin xout [6] [6] [7] [7 nc a 8 xout xin v ss dq6 dq5 dq4 v cc a 13 dq3 a 12 dq2 dq1 dq0 oe a 9 ce nc a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 11 a 7 a 14 a 15 a 16 nc nc nc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 a 10 v rtcbat we dq7 hsb int v ss v cc v cap v rtccap 45 46 47 48 nc nc nc nc 48 - ssop (x8) [5] [4] [4] [5] top view (not to scale) (not to scale) (not to scale) top view top view notes 4. address expansion for 2 mbit. nc pin not connected to die. 5. address expansion for 4 mbit. nc pin not connected to die. 6. address expansion for 8 mbit. nc pin not connected to die. 7. address expansion for 16 mbi t. nc pin not connected to die. [+] feedback cy14b101ka/cy14b101ma document #: 001-42880 rev. *d page 3 of 30 device operation the cy14b101ka/cy14b101ma nvsram is made up of two functional components paired in the same physical cell. these are a sram memory cell and a nonvolatile quantumtrap cell. the sram memory cell operates as a standard fast static ram. data in the sram is transferr ed to the nonvolatile cell (the store operation), or from the nonvolatile cell to the sram (the recall operation). using this unique architecture, all cells are stored and recalled in parallel. during the store and recall operations sram read and write operations are inhibited. the cy14b101ka/cy14b101ma supports infinite reads and writes similar to a typical sram. in addition, it provides infinite recall operations from the nonvolatile cells and up to 200k store operations. refer the truth table for sram operations on page 23 for a complete description of read and write modes. sram read the cy14b101ka/cy14b101ma performs a read cycle whenever ce and oe are low, and we and hsb are high. the address specified on pins a 0-16 or a 0-15 determines which of the 131,072 data bytes or 65,536 words of 16 bits each are accessed. byte enables (bhe , ble ) determine which bytes are enabled to the output, in the case of 16-bit words. when the read is initiated by an address transition, the outputs are valid after a delay of t aa (read cycle #1). if the read is initiated by ce or oe , the outputs are valid at t ace or at t doe , whichever is later (read cycle #2). the data output repeatedly responds to address changes within the t aa access time without the need for transi- tions on any control input pins. this remains valid until another address change or until ce or oe is brought high, or we or hsb is brought low. sram write a write cycle is performed when ce and we are low and hsb is high. the address inputs must be stable before entering the write cycle and must re main stable until ce or we goes high at the end of the cycle. the data on the common i/o pins io 0-7 are written into the memory if it is valid t sd before the end of a we- controlled write, or before the end of an ce -controlled write. the byte enable inputs (bhe , ble ) determine which bytes are written, in the case of 16-bit words . it is recommended that oe be kept high during the entire write cycle to avoid data bus contention on common i/o lines. if oe is left low, internal circuitry turns off the output buffers t hzwe after we goes low. autostore operation the cy14b101ka/cy14b101ma stores data to the nvsram using one of three storage operations. these three operations are: hardware store, activated by the hsb ; software store, activated by an address sequence; autostore, on device power down. the autostore operation is a unique feature of quantumtrap technology and is enabled by default on the cy14b101ka/cy14b101ma. during normal operation, the device draws current from v cc to charge a capacitor connected to the v cap pin. this stored charge is used by the chip to perform a single store operation. if the voltage on the v cc pin drops below v switch , the part automatically disconnects the v cap pin from v cc . a store operation is initiated with power provided by the v cap capacitor. note if the capacitor is not connected to v cap pin, autostore must be disabled using the soft sequence specified in preventing autostore on page 5. in case autostore is enabled without a capacitor on v cap pin, the device attempts an autostore operation without sufficient char ge to complete the store. this may corrupt the data stored in nvsram. figure 2. autostore mode figure 2 shows the proper connection of the storage capacitor (v cap ) for automatic store operation. refer to dc electrical characteristics on page 15 for the size of the v cap . the voltage int output interrupt output . programmable to respond to the clock alarm, the watchdog timer, and the power monitor. also programmable to either active high (push or pull) or low (open drain). v ss ground ground for the device . must be connected to the ground of the system. v cc power supply power supply inputs to the device . 3.0v +20%, ?10% hsb input/output hardware store busy (hsb ) . when low this output indicates that a hardware store is in progress. when pulled low external to the chip, it initiates a nonvolatile store operation. a weak internal pull up resistor keeps this pin high if not connected (connection optional). after each store operation, hsb is driven high for short time with standard output high current. v cap power supply autostore capacitor . supplies power to the nvsram during power loss to store data from sram to nonvolatile elements. pin definitions (continued) pin name i/o type description 0.1uf v cc 10kohm v cap we v cap v ss v cc [+] feedback cy14b101ka/cy14b101ma document #: 001-42880 rev. *d page 4 of 30 on the v cap pin is driven to v cc by a regulator on the chip. place a pull up on we to hold it inactive during power up. this pull up is only effective if the we signal is tristate during power up. many mpus tristate their controls on power up. this must be verified when using the pull up. when the nvsram comes out of power-on-recall, the mpu must be active or the we held inactive until the mpu comes out of reset. to reduce unnecessary nonvolatile stores, autostore and hardware store operations are ignored unless at least one write operation has taken place since the most recent store or recall cycle. software initia ted store cycles are performed regardless of whether a write operation has taken place. the hsb signal is monitored by the system to detect if an autostore cycle is in progress. hardware store (hsb ) operation the cy14b101ka/cy14b101ma provides the hsb pin to control and acknowledge the store operations. the hsb pin is used to request a hardware store cycle. when the hsb pin is driven low, the cy14b1 01ka/cy14b101ma conditionally initiates a store operation after t delay . an actual store cycle begins only if a write to the sram has taken place since the last store or recall cycle. the hsb pin also acts as an open drain driver that is internally driven low to indicate a busy condition when the store (initiated by any means) is in progress. sram write operations that are in progress when hsb is driven low by any means are given time (t delay ) to complete before the store operation is initiat ed. however, any sram write cycles requested after hsb goes low are inhibited until hsb returns high. in case the write latch is not set, hsb is not driven low by the cy14b101ka/cy14b101ma. but any sram read and write cycles are inhibited until hsb is returned high by mpu or other external source. during any store operation, rega rdless of how it is initiated, the cy14b101ka/cy14b101ma c ontinues to drive the hsb pin low, releasing it only when the store is complete. upon completion of the store operation, the cy14b101ka/cy14b101ma remains disabled until the hsb pin returns high. leave the hsb unconnected if it is not used. hardware recall (power up) during power up or after any low power condition (v cc cy14b101ka/cy14b101ma document #: 001-42880 rev. *d page 6 of 30 best practices nvsram products have been used effectively for over 15 years. while ease-of-use is one of t he product?s main system values, experience gained working with hundreds of applications has resulted in the following suggestions as best practices: the nonvolatile cells in this nvsram product are delivered from cypress with 0x00 written in all cells. incoming inspection routines at customer or co ntract manufacturer?s sites sometimes reprogram these values. final nv patterns are typically repeating patterns of aa, 55, 00, ff, a5, or 5a. end product?s firmware should not assume an nv array is in a set programmed state. routines that check memory content values to determine first time system configuration, cold or warm boot status, and so on should always program a unique nv pattern (that is, complex 4-byte pattern of 46 e6 49 53 hex or more random bytes) as part of the final system manufac- turing test to ensure these system routines work consistently. power up boot firmware routines should rewrite the nvsram into the desired state (for exam ple, autostore enabled). while the nvsram is shipped in a preset state, best practice is to again rewrite the nvsram into th e desired state as a safeguard against events that might flip the bit inadvertently such as program bugs and incoming inspection routines. the v cap value specified in this data sheet includes a minimum and a maximum value size. best practice is to meet this requirement and not exceed the maximum v cap value because the nvsram internal algorithm calculates v cap charge and discharge time based on this max v cap value. customers that want to use a larger v cap value to make sure there is extra store charge and store time should discuss their v cap size selection with cypress to understand any impact on the v cap voltage level at the end of a t recall period. [+] feedback cy14b101ka/cy14b101ma document #: 001-42880 rev. *d page 7 of 30 data protection the cy14b101ka/cy14b101ma prot ects data from corruption during low voltage conditions by inhibiting all externally initiated store and write operations. the low voltage condition is detected when v cc is less than v switch . if the cy14b101ka/cy14b101ma is in a write mode (both ce and we are low) at power up, after a recall or store, the write is inhibited until the sram is enabled after t lzhsb (hsb to output active). this protects against inadvertent writes during power up or brown out conditions. noise considerations refer to cy application note an1064 . real time clock operation nvtime operation the cy14b101ka/cy14b101ma offers internal registers that contain clock, alarm, watchdog, interrupt, and control functions. internal double buffering of the clock and timer information registers prevents accessing transitional internal clock data during a read or write oper ation. double buffering also circumvents disrupting normal timing counts or the clock accuracy of the internal clock when accessing clock data. clock and alarm registers store data in bcd format. rtc functionality is described with respect to cy14b101ka in the following sections. the same description applies to cy14b101ma, except for the rtc register addresses. the rtc register addresses for cy14b 101ka range from 0x1fff0 to 0x1ffff, while those for cy14b101ma range from 0x0fff0 to 0x0ffff. refer to table 3 on page 11 and ta b l e 4 on page 12 for a detailed register map description. clock operations the clock registers maintain time up to 9,999 years in one second increments. the time can be set to any calendar time and the clock automatically keeps track of days of the week and month, leap years, and century transitions. there are eight registers dedicated to the clock functions, which are used to set time with a write cycle and to read time during a read cycle. these registers contain the time of day in bcd format. bits defined as ?0? are currently not used and are reserved for future use by cypress. reading the clock the double buffered rtc register structure reduces the chance of reading incorrect data from the clock. stop internal updates to the cy14b101ka time keeping registers before reading clock data, to prevent reading of data in transition. stopping the register updates does not affect clock accuracy. the updating process is stopped by writing a ?1? to the read bit ?r? (in the flags register at 0x1fff0), and does not restart until a ?0? is written to the read bit. the rtc registers are then read while the internal clock continues to run. after a ?0? is written to the read bit (?r?), all rtc registers are simultaneously updated within 20 ms. setting the clock setting the write bit ?w? (in the flag s register at 0x1fff0) to a ?1? stops updates to the time keeping registers and enables the time to be set. the correct day, date, and time is then written into the registers and must be in 24-hour bcd format. the time written is referred to as the ?base time?. this value is stored in nonvol- atile registers and used in the calculation of the current time. resetting the write bit to ?0? transfers the values of timekeeping registers to the actual clock counters, after which the clock resumes normal operation. if the time written to the timekeeping registers is not in the correct bcd format, each invalid nibble of the rtc registers continue counting to 0xf before rolling over to 0x0 after which rtc resumes normal operation. note the values entered in the timekeeping, alarm, calibration, and interrupt registers need a store operation to be saved in nonvolatile memory. therefore, while working in autostore disabled mode, the user must perform a store operation after writing into the rtc registers for the rtc to work correctly. backup power the rtc in the cy14b101ka is intended for permanently powered operation. the v rtccap or v rtcbat pin is connected depending on whether a capacitor or battery is chosen for the application. when the primary power, v cc , fails and drops below v switch the device switches to the backup power supply. the clock oscillator uses very little current, which maximizes the backup time available from the backup source. regardless of the clock operation with the primary source removed, the data stored in the nvsram is secure, having been stored in the nonvolatile elements when power was lost. during backup operation, the cy14b101ka consumes 350 nanoamps (typ) at room temper ature. the user must choose capacitor or battery values according to the application. backup time values based on maximum current specifications are shown in the following table. nominal backup times are approximately two times longer. using a capacitor has the obvious advantage of recharging the backup source each time the syst em is powered up. if a battery is used, a 3v lithium is recommended and the cy14b101ka sources current only from the battery when the primary power is removed. however, the battery is not recharged at any time by the cy14b101ka. the battery capacity must be chosen for total anticipated cumulative down time required over the life of the system. table 2. rtc backup time capacitor value backup time 0.1f 72 hours 0.47f 14 days 1.0f 30 days [+] feedback cy14b101ka/cy14b101ma document #: 001-42880 rev. *d page 8 of 30 stopping and starting the oscillator the oscen bit in the calibration register at 0x1fff8 controls the enable and disable of the oscill ator. this bit is nonvolatile and is shipped to customers in the ?e nabled? (set to 0) state. to preserve the battery life when the system is in storage, oscen must be set to ?1?. this turns off the oscillator circuit, extending the battery life. if the oscen bit goes from disabled to enabled, it takes approximately one second (two seconds maximum) for the oscillator to start. while system power is off, if t he voltage on the backup supply (v rtccap or v rtcbat ) falls below their respective minimum level, the oscillator may fail.the cy14b101ka has the ability to detect oscillator failure when system power is restor ed. this is recorded in the oscf (oscillator failed bit) of the flags register at the address 0x1fff0. when the device is powered on (v cc goes above v switch ) the oscen bit is checked for ?enabled? status. if the oscen bit is enabled and the oscillator is not active within the first 5 ms , the oscf bit is set to ?1?. the system must check for this condition and then write ?0? to clear the flag. note that in addition to setting the oscf flag bit, the time registers are reset to the ?base time? (see setting the clock on page 7), which is the value last written to the time keeping registers. the control or calibration registers and the oscen bit are not affected by the ?oscillator failed? condition. reset the value of oscf to ?0? when the time registers are written for the first time. this initializes the state of this bit which may have become set when the syst em was first powered on. to reset oscf, set the write bit ?w? (in the flags register at 0x1fff0) to a ?1? to enable writes to the flag register. write a ?0? to the oscf bit and reset the write bit to ?0? to disable writes. calibrating the clock the rtc is driven by a quartz controlled crystal with a nominal frequency of 32.768 khz. clock accuracy depends on the quality of the crystal and calibration. the crystals available in market typically have an error of + 20 ppm to + 35 ppm. however, cy14b101ka employs a calibration circuit that improves the accuracy to +1/?2 ppm at 25c. this implies an error of +2.5 seconds to -5 seconds per month. the calibration circuit adds or subt racts counts from the oscillator divider circuit to achieve this accuracy. the number of pulses that are suppressed (subtracted, negative calibration) or split (added, positive calibration) depends upon the value loaded into the five calibration bits found in calibra tion register at 0x1fff8. the calibration bits occupy the five lo wer order bits in the calibration register. these bits are set to represent any value between ?0? and 31 in binary form. bit d5 is a sign bit, where a ?1? indicates positive calibration and a ?0? indicates negative calibration. adding counts speeds the clock up and subtracting counts slows the clock down. if a binary ?1? is loaded into the register, it corre- sponds to an adjustment of 4.068 or ?2.034 ppm offset in oscil- lator error, depending on the sign. calibration occurs within a 64-minute cycl e. the first 62 minutes in the cycle may, once per minute, have one second shortened by 128 or lengthened by 256 oscillator cycles. if a binary ?1? is loaded into the register, only the first two minutes of the 64-minute cycle are modified. if a binary 6 is loaded, the first 12 are affected, and so on. therefore, each calibration step has the effect of adding 512 or subtracting 256 oscillator cycles for every 125,829,120 ac tual oscillator cycles, that is, 4.068 or ?2.034 ppm of adjustment per calibration step in the calibration register. to determine the required calibration, the cal bit in the flags register (0x1fff0) must be set to ?1?. this causes the int pin to toggle at a nominal frequency of 512 hz. any deviation measured from the 512 hz indicates the degree and direction of the required correction. for example, a reading of 512.01024 hz indicates a +20 ppm error. hence, a decimal value of ?10 (001010b) must be loaded into the calibration register to offset this error. note setting or changing the calibration register does not affect the test output frequency. to set or clear cal, set the writ e bit ?w? (in the flags register at 0x1fff0) to ?1? to enable writes to the flag register. write a value to cal, and then reset the write bit to ?0? to disable writes. alarm the alarm function compares user programmed values of alarm time and date (stored in the registers 0x1fff1-5) with the corre- sponding time of day and date values. when a match occurs, the alarm internal flag (af) is set and an interrupt is generated on int pin if alarm interrupt enable (aie) bit is set. there are four alarm match fields - date, hours, minutes, and seconds. each of these fields has a match bit that is used to determine if the field is used in the alarm match logic. setting the match bit to ?0? indicates that the corresponding field is used in the match process. depending on the match bits, the alarm occurs as specifically as once a month or as frequently as once every minute. selecting none of the match bits (all 1s) indicates that no match is required and therefore, alarm is disabled. selecting all match bits (all 0s) causes an exact time and date match. there are two ways to detect an alarm event: by reading the af flag or monitoring the int pin. the af flag in the flags register at 0x1fff0 indicates that a date or time match has occurred. the af bit is set to ?1? when a match occurs. reading the flags register clears the alarm flag bit (and all others). a hardware interrupt pin may also be used to detect an alarm event. to set, clear or enable an alarm, set the ?w? bit (in flags register - 0x1fff0) to ?1? to enable writes to alarm registers. after writing the alarm value, clear the ?w? bit back to ?0? for the changes to take effect. note cy14b101ka requires the alarm match bit for seconds (0x1fff2 - d7) to be set to ?0? for proper operation of alarm flag and interrupt. watchdog timer the watchdog timer is a free running down counter that uses the 32 hz clock (31.25 ms) deri ved from the crystal oscillator. the oscillator must be running for the watchdog to function. it begins counting down from the value loaded in the watchdog timer register. the timer consists of a loadable register and a free running counter. on power up, the watchdog time out value in register 0x1fff7 is loaded into the counter load register. counting begins on power up and restarts from the loadable value any time the watchdog strobe (wds) bit is set to ?1?. the counter is compared to the terminal value of ?0?. if the counter reaches this [+] feedback cy14b101ka/cy14b101ma document #: 001-42880 rev. *d page 9 of 30 value, it causes an internal flag and an optional interrupt output. you can prevent the time out interrupt by setting wds bit to ?1? prior to the counter reaching ?0?. this causes the counter to reload with the watchdog time out value and to be restarted. as long as the user sets the wds bi t prior to the counter reaching the terminal value, the interrupt and wdt flag never occur. new time out values are written by setting the watchdog write bit to ?0?. when the wdw is ?0?, new writes to the watchdog time out value bits d5-d0 are enabled to modify the time out value. when wdw is ?1?, writes to bits d5-d0 are ignored. the wdw function enables a user to set the wds bit without concern that the watchdog timer value is modified. a logical diagram of the watchdog timer is shown in figure 3 . note that setting the watchdog time out value to ?0? disables the watchdog function. the output of the watchdog timer is the flag bit wdf that is set if the watchdog is allowed to time out. if the watchdog interrupt enable (wie) bit in the interrupt register is set, a hardware interrupt on int pin is also generated on watchdog timeout. the flag and the hardware interrupt are both cleared when user reads the flags registers. . power monitor the cy14b101ka provides a power management scheme with power fail interrupt capability. it also controls the internal switch to backup power for the clock and protects the memory from low v cc access. the power monitor is based on an internal band gap reference circuit that compares the v cc voltage to v switch threshold. as described in the autostore operation on page 3, when v switch is reached as v cc decays from power loss, a data store operation is initiated from sram to the nonvolatile elements, securing the last sram data state. power is also switched from v cc to the backup supply (battery or capacitor) to operate the rtc oscillator. when operating from the backup source, read and write opera- tions to nvsram are inhibited and the clock functions are not available to the user. the clock continues to operate in the background. the updated clock data is available to the user t hrecall delay after v cc is restored to the device (see autostore/power up recall on page 20). interrupts the cy14b101ka has flags register, interrupt register and interrupt logic that can signal interrupt to the microcontroller. there are three potential sources for interrupt: watchdog timer, power monitor, and alarm timer. each of these can be individually enabled to drive the int pin by appropriate setting in the interrupt register (0x1fff6). in addition, each has an associated flag bit in the flags register (0x1fff0) that the host processor uses to determine the cause of the interrupt. the int pin driver has two bits that specify its behavior when an interrupt occurs. an interrupt is raised only if both a flag is raised by one of the three sources and the respective interrupt enable bit in interrupts register is enabled (set to ?1?). after an interrupt source is active, two programmable bits, h/l and p/l, determine the behavior of the output pin driver on int pin. these two bits are located in the interrupt register and can be used to drive level or pulse mode output from the int pin. in pulse mode, the pulse width is internally fixed at approximatel y 200 ms. this mode is intended to reset a host microcontroller. in the level mode, the pin goes to its active polarity until the flags register is read by the user. this mode is used as an interrupt to a host microcontroller. the control bits are summarized in the following section. interrupts are only generated while working on normal power and are not triggered when system is running in backup power mode. note cy14b101ka generates valid interrupts only after the powerup recall sequence is completed. all events on int pin must be ignored for t hrecall duration after powerup. interrupt register watchdog interrupt enable - wie . when set to ?1?, the watchdog timer drives the int pin and an internal flag when a watchdog time out occurs. when wie is set to ?0?, the watchdog timer only affects the wdf flag in flags register. alarm interrupt enable - aie . when set to ?1?, the alarm match drives the int pin and an internal flag. when aie is set to ?0?, the alarm match only affects the af flag in flags register. power fail interrupt enable - pfe . when set to ?1?, the power fail monitor drives the pin and an internal flag. when pfe is set to ?0?, the power fail monitor only affects the pf flag in flags register. high/low - h/l . when set to a ?1?, the int pin is active high and the driver mode is push pull. the int pin drives high only when v cc is greater than v switch . when set to a ?0?, the int pin is active low and the drive mode is open drain. the int pin must be pulled up to vcc by a 10k resistor while using the interrupt in active low mode. pulse/level - p/l . when set to a ?1? and an interrupt occurs, the int pin is driven for approximately 200 ms. when p/l is set to a ?0?, the int pin is driven high or low (determined by h/l) until the flags or control register is read. when an enabled interrupt source activates the int pin, an external host reads the flags registers to determine the cause. all flags are cleared when the regi ster is read. if the int pin is programmed for level mode, then the condition clears and the int pin returns to its inactive state. if the pin is programmed for pulse mode, then reading the flag also clears the flag and the pin. the pulse does not complete its specified duration if the flags register is read. if the in t pin is used as a host reset, then the flags register is not read during a reset. figure 3. watchdog timer block diagram 1 hz oscillator clock divider counter zero compare wdf wds load register wdw d q q watchdog register write to watchdog register 32 hz 32,768 khz [+] feedback cy14b101ka/cy14b101ma document #: 001-42880 rev. *d page 10 of 30 flags register the flag register has three flag bits: wdf, af, and pf, which can be used to generate an interrupt. these flags are set by the watchdog timeout, alarm match, or power fail monitor respec- tively. the processor can either poll th is register or enable inter- rupts to be informed when a flag is set. these flags are automat- ically reset when the register is read. the flags register is automatically loaded with the value 0x00 on power up (except for the oscf bit; see stopping and starting the oscillator on page 8). figure 4. rtc recommended component configuration figure 5. interrupt block diagram x out x in y1 c2 c1 recommended values y 1 = 32.768 khz (12.5 pf) c 1 = 10 pf c 2 = 67 pf note: the recommended values for c1 and c2 include board trace capacitance. watchdog timer power monitor clock alarm vint wdf wie pf pfe af aie p/l pin driver h/l int v cc v ss wdf - watchdog timer flag wie - watchdog interrupt pf - power fail flag pfe - power fail enable af - alarm flag aie - alarm interrupt enable p/l - pulse level h/l - high/low enable [+] feedback cy14b101ka/cy14b101ma document #: 001-42880 rev. *d page 11 of 30 table 3. rtc register map [10, 11, 12] register bcd format data [11] function/range cy14b101ka cy14b101ma d7 d6 d5 d4 d3 d2 d1 d0 0x1ffff 0x0ffff 10s years years years: 00?99 0x1fffe 0x0fffe 0 0 0 10s months months months: 01?12 0x1fffd 0x0fffd 0 0 10s day of month day of month day of month: 01?31 0x1fffc 0x0fffc 0 0 0 0 0 day of week day of week: 01?07 0x1fffb 0x0fffb 0 0 10s hours hours hours: 00?23 0x1fffa 0x0fffa 0 10s minutes minutes minutes: 00?59 0x1fff9 0x0fff9 0 10s seconds seconds seconds: 00?59 0x1fff8 0x0fff8 oscen (0) 0cal sign (0) calibration (00000) calibration values [13] 0x1fff7 0x0fff7 wds (0) wdw (0) wdt (000000) watchdog [13] 0x1fff6 0x0fff6 wie (0) aie (0) pfe (0) 0 h/l (1) p/l (0) 0 0 interrupts [13] 0x1fff5 0x0fff5 m (1) 0 10s alarm date alarm day alarm, day of month: 01?31 0x1fff4 0x0fff4 m (1) 0 10s alarm hours alarm hours alarm, hours: 00?23 0x1fff3 0x0fff3 m (1) 10 alarm minutes a larm minutes alarm, minutes: 00?59 0x1fff2 0x0fff2 m (1) 10 alarm seconds alarm, seconds alarm, seconds: 00?59 0x1fff1 0x0fff1 10s centuries centuries centuries: 00?99 0x1fff0 0x0fff0 wdf af pf oscf 0 cal (0) w (0) r (0) flags [13] notes 10. upper byte d15-d8 (cy14b101ma) of rtc registers are reserved for future use. 11. the unused bits of rtc registers are reserved for future use and should be set to ?0?. 12. ( ) designates values shipped from the factory. 13. this is a binary value, not a bcd value. [+] feedback cy14b101ka/cy14b101ma document #: 001-42880 rev. *d page 12 of 30 table 4. register map detail register description cy14b101ka cy14b101ma 0x1ffff 0x0ffff time keeping - years d7 d6 d5 d4 d3 d2 d1 d0 10s years years contains the lower two bcd digits of the year. lower nibble (four bits) contains the value for years; upper nibble (four bits) contains the value for 10s of years. each nibble operates from 0 to 9. the range for the register is 0?99. 0x1fffe 0x0fffe time keeping - months d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 10s month months contains the bcd digits of the month. lower nibbl e (four bits) contains the lower digit and operates from 0 to 9; upper nibble (one bit) contains th e upper digit and operates from 0 to 1. the range for the register is 1?12. 0x1fffd 0x0fffd time keeping - date d7 d6 d5 d4 d3 d2 d1 d0 0 0 10s day of month day of month contains the bcd digits for the date of the month. lower nibble (four bits) contains the lower digit and operates from 0 to 9; upper nibble (two bits) contains the 10s digit and operates from 0 to 3. the range for the register is 1?31. leap years are automatically adjusted for. 0x1fffc 0x0fffc time keeping - day d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 0 0 day of week lower nibble (three bits) contains a value that co rrelates to day of the week. day of the week is a ring counter that counts from 1 to 7 then return s to 1. the user must assign meaning to the day value, because the day is not integrated with the date. 0x1fffb 0x0fffb time keeping - hours d7 d6 d5 d4 d3 d2 d1 d0 0 0 10s hours hours contains the bcd value of hours in 24 hour format. lower nibble (four bits) contains the lower digit and operates from 0 to 9; upper nibble (two bits) contains the upper digit and operates from 0 to 2. the range for the register is 0?23. 0x1fffa 0x0fffa time keeping - minutes d7 d6 d5 d4 d3 d2 d1 d0 0 10s minutes minutes contains the bcd value of minutes. lower nibble (four bits) contains the lower digit and operates from 0 to 9; upper nibble (three bits) contains the upper minutes digit and operates from 0 to 5. the range for the register is 0?59. 0x1fff9 0x0fff9 time keeping - seconds d7 d6 d5 d4 d3 d2 d1 d0 0 10s seconds seconds contains the bcd value of seconds. lower nibble (f our bits) contains the lower digit and operates from 0 to 9; upper nibble (three bits) contains the upper digit and operates from 0 to 5. the range for the register is 0?59. [+] feedback cy14b101ka/cy14b101ma document #: 001-42880 rev. *d page 13 of 30 register description cy14b101ka cy14b101ma 0x1fff8 0x0fff8 calibration/control d7 d6 d5 d4 d3 d2 d1 d0 oscen 0 calibration sign calibration oscen oscillator enable. when set to 1, the oscillato r is stopped. when set to 0, the oscillator runs. disabling the oscillator saves battery or capacitor power during storage. calibration sign determines if the calibration adjustment is applied as an addition (1) to or as a subtraction (0) from the time-base. calibration these five bits cont rol the calibration of the clock. 0x1fff7 0x0fff7 watchdog timer d7 d6 d5 d4 d3 d2 d1 d0 wds wdw wdt wds watchdog strobe. setting this bit to 1 reloads and restarts the watchdog timer. setting the bit to 0 has no effect. the bit is cleared automatically after the watchdog timer is reset. the wds bit is write only. reading it always returns a 0. wdw watchdog write enable. setting this bit to 1 disables any write to the watchdog timeout value (d5?d0). this allows the user to set the watchdog strobe bit without disturbing the timeout value. setting this bit to 0 allows bits d5?d0 to be wr itten to the watchdog regi ster when the next write cycle is complete. this function is explained in more detail in watchdog timer on page 8. wdt watchdog timeout selection. the watchdog timer in terval is selected by the 6-bit value in this register. it represents a multiplier of the 32 hz count (31.25 ms). the range of timeout value is 31.25 ms (a setting of 1) to 2 seconds (setting of 3 fh). setting the watchdog timer register to 0 disables the timer. these bits can be written only if the wdw bit was set to 0 on a previous cycle. 0x1fff6 0x0fff6 interrupt status/control d7 d6 d5 d4 d3 d2 d1 d0 wie aie pfe 0 h/l p/l 0 0 wie watchdog interrupt enable. when set to 1 and a watchdog timeout occurs, the watchdog timer drives the int pin and the wdf flag. when set to 0, the watchdog timeout affects only the wdf flag. aie alarm interrupt enable. when set to 1, the alarm match drives the int pin and the af flag. when set to 0, the alarm match only affects the af flag. pfe power fail enable. when set to 1, the power fail monitor drives the int pin and the pf flag. when set to 0, the power fail monitor affects only the pf flag. 0 reserved for future use h/l high/low. when set to 1, the int pin is driven ac tive high. when set to 0, the int pin is open drain, active low. p/l pulse/level. when set to 1, the int pin is driven ac tive (determined by h/l) by an interrupt source for approximately 200 ms. when set to 0, the int pin is driven to an active level (as set by h/l) until the flags register is read. 0x1fff5 0x0fff5 alarm - day d7 d6 d5 d4 d3 d2 d1 d0 m 0 10s alarm date alarm date contains the alarm value for the date of the mont h and the mask bit to select or deselect the date value. m match. when this bit is set to 0, the date value is used in the alarm match. setting this bit to 1 causes the match circuit to ignore the date value. table 4. register map detail (continued) [+] feedback cy14b101ka/cy14b101ma document #: 001-42880 rev. *d page 14 of 30 register description cy14b101ka cy14b101ma 0x1fff4 0x0fff4 alarm - hours d7 d6 d5 d4 d3 d2 d1 d0 m 0 10s alarm hours alarm hours contains the alarm value for the hours and the mask bit to select or deselect the hours value. m match. when this bit is set to 0, the hours value is used in the al arm match. setting this bit to 1 causes the match circuit to ignore the hours value. 0x1fff3 0x0fff3 alarm - minutes d7 d6 d5 d4 d3 d2 d1 d0 m 10s alarm minutes alarm minutes contains the alarm value for the minutes and the mask bit to select or deselect the minutes value. m match. when this bit is set to 0, the minutes val ue is used in the alarm match. setting this bit to 1 causes the match circuit to ignore the minutes value. 0x1fff2 0x0fff2 alarm - seconds d7 d6 d5 d4 d3 d2 d1 d0 m 10s alarm seconds alarm seconds contains the alarm value for the seconds and the mask bit to select or deselect the seconds? value. m match. when this bit is set to 0, the seconds valu e is used in the alarm match. setting this bit to 1 causes the match circuit to ignore the seconds value. 0x1fff1 0x0fff1 time keeping - centuries d7 d6 d5 d4 d3 d2 d1 d0 10s centuries centuries contains the bcd value of centuries. lower nibble (four bits) contains the lower digit and operates from 0 to 9; upper nibble (two bits) contains the upper digit and operates from 0 to 9. the range for the register is 0-99 centuries. 0x1fff0 0x0fff0 flags d7 d6 d5 d4 d3 d2 d1 d0 wdf af pf oscf 0 cal w r wdf watchdog timer flag. this read only bit is set to 1 when the watchdog timer is allowed to reach 0 without being reset by the user. it is cleared to 0 when the flags register is read or on power up af alarm flag. this read only bit is set to 1 when the time and date match the values stored in the alarm registers with the match bits = 0. it is cleared when the flags register is read or on power up. pf power fail flag. this read only bit is set to 1 when power falls below the power fail threshold v switch . it is cleared to 0 when the flags register is read or on power up. oscf oscillator fail flag. set to 1 on power up if the oscillator is enabled and not running in the first 5 ms of operation. this indicates that rtc backup power failed and clock value is no longer valid. this bit survives power cycle and is never cleared internally by th e chip. the user must check for this condition and write '0' to clear this flag. cal calibration mode. when set to 1, a 512 hz square wave is output on the int pin. when set to 0, the int pin resumes normal operation. this bit defaults to 0 (disabled) on power up. w write enable: setting the w bit to 1 freezes updates of the rtc registers. the user can then write to rtc registers, alarm registers, calibration register, interrupt re gister and flags register. setting the w bit to 0 transfers the contents of the rtc r egisters to the time keepin g counters if the time is changed (a new base time is loaded). this bit defaults to 0 on power up. r read enable: setting r bit to 1, stops clock updates to user rtc registers so that clock updates are not seen during the reading process. set r bit to 0 to resume clock updates to the holding register. setting this bit does not require w bit to be set to 1. this bit defaults to 0 on power up. table 4. register map detail (continued) [+] feedback cy14b101ka/cy14b101ma document #: 001-42880 rev. *d page 15 of 30 maximum ratings exceeding maximum ratings may impair the useful life of the device. these user guidelines are not tested. storage temperature ................................. ?65 c to +150 c maximum accumulated storage time at 150 c ambient temperature........................ 1000h at 85 c ambient temperature..................... 20 years ambient temperature wit h power applied.. ?55 c to +150 c supply voltage on v cc relative to gnd ..........?0.5v to 4.1v voltage applied to outputs in high-z state....................................... ?0.5v to v cc + 0.5v input voltage.............................................?0.5v to vcc+0.5v transient voltage (<20 ns) on any pin to ground potential .................. ?2.0v to v cc + 2.0v package power dissipation capability (t a = 25c) ................................................... 1.0w surface mount pb soldering temperature (3 seconds) .......................................... +260 c dc output current (1 output at a time, 1s duration).....15 ma static discharge voltage....... ........... ............ ............ > 2001v (per mil-std-883, method 3015) latch up current .............................................. ..... > 200 ma operating range range ambient temperature v cc industrial ?40 c to +85 c 2.7v to 3.6v dc electrical characteristics over the operating range (v cc = 2.7v to 3.6v) parameter description test conditions min typ [14] max unit v cc power supply voltage 2.7 3.0 3.6 v i cc1 average v cc current t rc = 25 ns t rc = 45 ns values obtained without output loads (i out = 0 ma) 70 52 ma ma i cc2 average v cc current during store all inputs don?t care, v cc = max. average current for duration t store 10 ma i cc3 [14] average v cc current at t rc = 200 ns, v cc (typ), 25c all i/p cycling at cmos levels. values obtained without output loads (i out = 0 ma). 35 ma i cc4 average v cap current during autostore cycle all inputs don?t care. average current for duration t store 5ma i sb v cc standby current ce > (v cc ? 0.2v). v in < 0.2v or > (v cc ? 0.2v). w bit set to ?0?. standby current level after non volatile cycle is complete. inputs are static. f = 0 mhz. 5ma i ix [15] input leakage current (except hsb ) v cc = max, v ss < v in < v cc ?1 +1 a input leakage current (for hsb ) v cc = max, v ss < v in < v cc ?100 +1 a i oz off state output leakage current v cc = max, v ss < v out < v cc , ce or oe > v ih or bhe /ble > v ih or we < v il ?1 +1 a v ih input high voltage 2.0 v cc + 0.5 v v il input low voltage v ss ? 0.5 0.8 v v oh output high voltage i out = ?2 ma 2.4 v v ol output low voltage i out = 4 ma 0.4 v v cap storage capacitor between v cap pin and v ss , 5v rated 61 68 180 f notes 14. typical values are at 25c, v cc = v cc (typ). not 100% tested. 15. the hsb pin has i out = -2 ua for v oh of 2.4v when both active high and low drivers are disabled. when they are enabled standard v oh and v ol are valid. this parameter is characterized but not tested. [+] feedback cy14b101ka/cy14b101ma document #: 001-42880 rev. *d page 16 of 30 ac test conditions input pulse levels ....................................................0v to 3v input rise and fall times (10% - 90%) ........................ < 3 ns input and output timing reference levels .................... 1.5v capacitance parameter [16] description test conditions max unit c in input capacitance t a = 25 c, f = 1 mhz, v cc = v cc (typ) 7pf c out output capacitance 7 pf thermal resistance parameter [16] description test conditions 48 ssop 44 tsop ii 54 tsop ii unit ja thermal resistance (junction to ambient) test conditions follow standard test methods and procedures for measuring thermal impedance, in accordance with eia/jesd51. 37.47 41.74 36.4 c/w jc thermal resistance (junction to case) 24.71 11.90 10.13 c/w figure 6. ac test loads 3.0v output 5 pf r1 r2 789 3.0v output 30 pf r1 r2 789 577 577 [14] max units v rtcbat rtc battery pin voltage 1.8 3.0 3.6 v i bak [17] rtc backup current t a (min) 350 na 25c 350 na t a (max) 500 na v rtccap [18] rtc capacitor pin voltage t a (min) 1.6 3.6 v 25c 1.5 3.0 3.6 v t a (max) 1.4 3.6 v tocs rtc oscillator time to start 1 2 sec r bkchg rtc backup capacitor charge current-limiting resistor 350 850 notes 16. these parameters are guaranteed by design and are not tested. 17. from either v rtccap or v rtcbat. 18. if v rtccap > 0.5v or if no capacitor is connected to v rtccap pin, the oscillator starts in tocs time. if a backup capacitor is connected and v rtccap < 0.5v, the capacitor must be allowed to charge to 0.5v for oscillator to start. [+] feedback cy14b101ka/cy14b101ma document #: 001-42880 rev. *d page 17 of 30 ac switching characteristics parameters description 25 ns 45 ns unit cypress parameters alt parameters min max min max sram read cycle t ace t acs chip enable access time 25 45 ns t rc [19] t rc read cycle time 25 45 ns t aa [20] t aa address access time 25 45 ns t doe t oe output enable to data valid 12 20 ns t oha [20] t oh output hold after address change 3 3 ns t lzce [16, 21] t lz chip enable to output active 3 3 ns t hzce [16, 21] t hz chip disable to output inactive 10 15 ns t lzoe [16, 21] t olz output enable to output active 0 0 ns t hzoe [16, 21] t ohz output disable to output inactive 10 15 ns t pu [16] t pa chip enable to power active 0 0 ns t pd [16] t ps chip disable to power standby 25 45 ns t dbe - byte enable to data valid 12 20 ns t lzbe [16] - byte enable to output active 0 0 ns t hzbe [16] - byte disable to output inactive 10 15 ns sram write cycle t wc t wc write cycle time 25 45 ns t pwe t wp write pulse width 20 30 ns t sce t cw chip enable to end of write 20 30 ns t sd t dw data setup to end of write 10 15 ns t hd t dh data hold after end of write 0 0 ns t aw t aw address setup to end of write 20 30 ns t sa t as address setup to start of write 0 0 ns t ha t wr address hold after end of write 0 0 ns t hzwe [16, 21, 22] t wz write enable to output disable 10 15 ns t lzwe [16, 21] t ow output active after end of write 3 3 ns t bw - byte enable to end of write 20 30 ns switching waveforms figure 7. sram read cycle #1: address controlled [19, 20, 23 ] address data output address valid previous data valid output data valid t rc t aa t oha notes 19. we must be high during sram read cycles. 20. device is continuously selected with ce , oe and bhe /ble low. 21. measured 200 mv from steady state output voltage. 22. if we is low when ce goes low, the outputs remain in the high impedance state. 23. hsb must remain high during read and write cycles. [+] feedback cy14b101ka/cy14b101ma document #: 001-42880 rev. *d page 18 of 30 figure 8. sram read cycle #2: ce and oe controlled [3, 19, 23] figure 9. sram write cycle #1: we controlled [3, 22, 23, 24] address valid address data output output data valid standby active high impedance ce oe bhe, ble i cc t hzce t rc t ace t aa t lzce t doe t lzoe t dbe t lzbe t pu t pd t hzbe t hzoe data output data input input data valid high impedance address valid address previous data t wc t sce t ha t bw t aw t pwe t sa t sd t hd t hzwe t lzwe we bhe, ble ce note 24. ce or we must be > v ih during address transitions. [+] feedback cy14b101ka/cy14b101ma document #: 001-42880 rev. *d page 19 of 30 figure 10. sram write cycle #2: ce controlled [3, 22, 23, 24] figure 11. sram write cycle #3: bhe and ble controlled [3, 22, 23, 24, 25] data output data input input data valid high impedance address valid address t wc t sd t hd bhe, ble we ce t sa t sce t ha t bw t pwe data output data input input data valid high impedance address valid address t wc t sd t hd bhe, ble we ce t sce t sa t bw t ha t aw t pwe (not applicable for rtc register writes) note 25. only ce and we controlled writes to rtc registers are allowed. ble pin must be held low before ce or we pin goes low for writes to rtc register. [+] feedback cy14b101ka/cy14b101ma document #: 001-42880 rev. *d page 20 of 30 autostore/power up recall parameters description cy14b101ka/cy14b101ma unit min max t hrecall [26] power up recall duration 20 ms t store [27] store cycle duration 8 ms t delay [28] time allowed to complete sram write cycle 25 ns v switch low voltage trigger level 2.65 v t vccrise [16] vcc rise time 150 s v hdis [16] hsb output disable voltage 1.9 v t lzhsb [16] hsb to output active time 5 s t hhhd [16] hsb high active time 500 ns switching waveforms figure 12. autostore or power up recall [29] v switch v hdis v vccrise t store t store t hhhd t hhhd t delay t delay t lzhsb t lzhsb t hrecall t hrecall hsb out autostore power- up recall read & write inhibited ( rwi ) power-up recall read & write brown out autostore power-up recall read & write power down autostore note note note v cc 27 27 30 notes 26. t hrecall starts from the time v cc rises above v switch. 27. if an sram write has not taken place since the last nonvolatile cycle, no au tostore or hardware store takes place 28. on a hardware store and autostore initiation, sram write operation continues to be enabled for time t delay . 29. read and wr ite cycles are ignored during store, recall, and while v cc is below v switch. 30. hsb pin is driven high to v cc only by internal 100 k resistor, hsb driver is disabled. [+] feedback cy14b101ka/cy14b101ma document #: 001-42880 rev. *d page 21 of 30 software controlled store/recall cycle parameters [31, 32] description 25 ns 45 ns unit min max min max t rc store/recall initiation cycle time 25 45 ns t sa address setup time 0 0 ns t cw clock pulse width 20 30 ns t ha address hold time 0 0 ns t recall recall duration 200 200 s t ss [33, 34] soft sequence processing time 100 100 s switching waveforms figure 13. ce & oe controlled software store/recall cycle [32] figure 14. autostore enable/disable cycle t rc t rc t sa t cw t cw t sa t ha t lzce t hzce t ha t ha t ha t store /t recall t hhhd t lzhsb high impedance address #1 address #6 address ce oe hsb(storeonly) dq (data) rwi t delay note 35 t rc t rc t sa t cw t cw t sa t ha t lzce t hzce t ha t ha t ha t delay address #1 address #6 address ce oe dq (data) t ss note 35 notes 31. the software sequence is clocked with ce controlled or oe controlled reads. 32. the six consecutive addresses must be read in the order listed in tab l e 1 . we must be high during all six consecutive cycles. 33. this is the amount of time it takes to take action on a soft sequence command. vcc power must remain high to effectively reg ister command. 34. commands such as store and recall lock out i/o until operation is complete which further incr eases this time. see the specif ic command. 35. dq output data at the sixth read may be invalid since the output is disabled at t delay time. [+] feedback cy14b101ka/cy14b101ma document #: 001-42880 rev. *d page 22 of 30 hardware store cycle parameters description cy14b101ka/cy14b101ma unit min max t dhsb hsb to output active time when write latch not set 25 ns t phsb hardware store pulse width 15 ns switching waveforms figure 15. hardware store cycle [27] figure 16. soft sequence processing [33, 34] t phsb t phsb t delay t dhsb t delay t store t hhhd t lzhsb write latch set write latch not set hsb (in) hsb (out) dq (data out) rwi hsb (in) hsb (out) rwi hsb pin is driven high to v cc only by internal sram is disabled as long as hsb (in) is driven low. hsb driver is disabled t dhsb 100kohm resistor, address #1 address #6 address #1 address #6 soft sequence command t ss t ss ce address v cc t sa t cw soft sequence command t cw [+] feedback cy14b101ka/cy14b101ma document #: 001-42880 rev. *d page 23 of 30 truth table for sram operations hsb must remain high for sram operations. table 5. truth table for x8 configuration ce we oe inputs/outputs [2] mode power h x x high z deselect/power down standby l h l data out (dq 0 ?dq 7 ) read active l h h high z output disabled active l l x data in (dq 0 ?dq 7 ) write active table 6. truth table for x16 configuration ce we oe bhe [3] ble [3] inputs/outputs [2] mode power h x x x x high-z deselect/power down standby l x x h h high-z output disabled active l h l l l data out (dq 0 ?dq 15 ) read active l h l h l data out (dq 0 ?dq 7 ) dq 8 ?dq 15 in high-z read active l h l l h data out (dq 8 ?dq 15 ) dq 0 ?dq 7 in high-z read active l h h l l high-z output disabled active l h h h l high-z output disabled active l h h l h high-z output disabled active l l x l l data in (dq 0 ?dq 15 ) write active l l x h l data in (dq 0 ?dq 7 ) dq 8 ?dq 15 in high-z write active l l x l h data in (dq 8 ?dq 15 ) dq 0 ?dq 7 in high-z write active [+] feedback cy14b101ka/cy14b101ma document #: 001-42880 rev. *d page 24 of 30 part numbering nomenclature option: t - tape and reel blank - std. speed: 25 - 25 ns data bus: k - x8 + rtc m - x16 + rtc density: 101 - 1 mb voltage: b - 3.0v cypress cy 14 b 101 k a -zsp 25 x i t 14 - nvsram temperature: i - industrial (?40 to 85c) pb-free package: zsp - 44 tsop ii 45 - 45 ns zsp - 54 tsop ii die revision: blank - no rev a - 1 st rev spp - 48 ssop [+] feedback cy14b101ka/cy14b101ma document #: 001-42880 rev. *d page 25 of 30 ordering information speed (ns) ordering code package diagram package type operating range 25 cy14b101ka-zs25xit 51-85087 44-pin tsopii industrial cy14b101ka-zs25xi 51-85087 44-pin tsopii CY14B101MA-ZSP25XIT 51-85160 54-pin tsopii cy14b101ma-zsp25xi 51-85160 54-pin tsopii cy14b101ka-sp25xit 51-85061 48-pin ssop cy14b101ka-sp25xi 51-85061 48-pin ssop 45 cy14b101ka-zs45xit 51-85087 44-pin tsopii cy14b101ka-zs45xi 51-85087 44-pin tsopii cy14b101ma-zsp45xit 51-85160 54-pin tsopii cy14b101ma-zsp45xi 51-85160 54-pin tsopii cy14b101ka-sp45xit 51-85061 48-pin ssop cy14b101ka-sp45xi 51-85061 48-pin ssop all the above parts are pb-free. [+] feedback cy14b101ka/cy14b101ma document #: 001-42880 rev. *d page 26 of 30 package diagrams figure 17. 44-pin tsop ii (51-85087) figure 18. 54-pin tsop ii (51-85160) max min. dimension in mm (inch) 11.938 (0.470) plane seating pin 1 i.d. 44 1 18.517 (0.729) 0.800 bsc 0-5 0.400(0.016) 0.300 (0.012) ejector pin r g o k e a x s 11.735 (0.462) 10.058 (0.396) 10.262 (0.404) 1.194 (0.047) 0.991 (0.039) 0.150 (0.0059) 0.050 (0.0020) (0.0315) 18.313 (0.721) 10.058 (0.396) 10.262 (0.404) 0.597 (0.0235) 0.406 (0.0160) 0.210 (0.0083) 0.120 (0.0047) base plane 0.10 (.004) 22 23 top view bottom view 51-85087-*a 51-85160-** [+] feedback cy14b101ka/cy14b101ma document #: 001-42880 rev. *d page 27 of 30 figure 19. 48-pin ssop (51-85061) package diagrams (continued) [+] feedback cy14b101ka/cy14b101ma document #: 001-42880 rev. *d page 28 of 30 document history page document title: cy14b101ka/cy14b101ma 1 mbit (128 k x 8/64k x 16) nvsram with real time clock document number: 001-42880 rev. ecn no. submission date orig. of change description of change ** 2050747 see ecn unc/pyrs new data sheet *a 2607447 11/18/2008 gvch/aesa removed 15 ns access sp eed, updated ?features?, added cy14b101ma (x16) part, changed title to ?cy14b101ka/cy14 b101ma 1 mbit (128k x 8/64k x 16) nvsram with real-time-clock?. added 54-pin tsop ii package related information, updated logic block diagram, added footnote 1 and 2. pin definition: updated we , hsb and nc pin description. page 4: updated sram read, sram write, autostore operation description, page 4: updated software store and software recall description updated figure 2, page 4: updated hard ware store operation and hardware recall (power up) description footnote 1 and 10 referenced for mode selection table added footnote 10, upd ated footnote 8 and 9 page 6: updated data protection description page 6: updated starting and stopp ing the oscillator description page 7: updated calibrating the clock description page 8: added flags register updated table 4, added footnote 12 and 13 updated register map detail table 5 maximum ratings: added max. accumulated storage time changed output short circuit current parameter name to dc output current changed i cc2 from 6 ma to 10 ma changed i cc3 from 15 ma to 35 ma changed i cc4 from 6 ma to 5 ma changed i sb from 3 ma to 5 ma added i ix for hsb updated i cc1, i cc3, i sb and i oz test conditions changed v cap voltage min value from 68uf to 61uf added v cap voltage max value to 180uf updated footnote 14 a nd 15, added footnote 16 added data retention and endurance table added thermal resistance value to 44/54 tsop ii packages updated input rise and fall time in ac test conditions changed v rtccap min value from 1.2 to 1.5v for industrial commercial temperature changed v rtccap min value from 2.7 to 3.6v for industrial commercial temperature updated rtc recommended component configuration values updated tocs value for minimum and room temperature from 10 and 5sec to 2 and 1sec resp. referenced footnote 22 to t oha parameter updated all switching waveforms updated footnote 22 , added footnote 25 added figure 11 (sram write cycle:bhe and ble controlled) changed t store max value from 15ms to 8ms updated t delay value added v hdis , t hhhd and t lzhsb parameters updated footnote 29, ad ded footnote 31 and 32 software controlled store/recall table: changed t as to t sa changed t ghax to t ha, changed t ha value from 1ns to 0ns added figure 14 added t dhsb parameter, changed t hlhx to t phsb updated t ss from 70 us to 100 us, added truth table for sram operations updated ordering information and part numbering nomenclature [+] feedback cy14b101ka/cy14b101ma document #: 001-42880 rev. *d page 29 of 30 *b 2654484 02/05/09 gvch/pyrs changed the data sheet from advance information to preliminary changed x 1 , x 2 pin names to x out , x in respectively updated real time clock operation description added footnotes 11 and 12 added default values to rtc register map? table 3 updated flag register description in register map detail? table 4 changed c1, c2 values to 21pf, 21pf respectively changed i bak value from 350 na to 450 na at hot temperature changed v rtccap typical value from 2.4v to 3.0v referenced note 15 to parameters t lzce , t hzce , t lzoe, t hzoe, t lzbe, t lzwe, t hzwe- and t hzbe added footnote 24 updated figure 13 *c 2733909 07/09/09 gvch/aesa page 3; added note to autost ore operation description page 4; updated hardware store (hsb ) operation description page 4; updated software store operation description added best practices changed c1, c2 values to 10pf, 67pf respectively changed i bak and v rtccap parameter values added r bkchg parameter updated v hdis parameter description updated t delay parameter description updated footnote 28 and added footnote 35 *d 2757375 08/28/09 gvch moved datasheet status from preliminary to final removed commercial temperature related specs removed 20ns access speed related specs updated thermal resistance values for all the packages changed v rtcbat max value from 3.3v to 3.6v changed r bkchg min value from 450 to 350 updated footnote 18 document title: cy14b101ka/cy14b101ma 1 mbit (128 k x 8/64k x 16) nvsram with real time clock document number: 001-42880 rev. ecn no. submission date orig. of change description of change [+] feedback document #: 001-42880 rev. *d revised august 28, 2009 page 30 of 30 all products and company names mentioned in this document are the trademarks of their respective holders. cy14b101ka/cy14b101ma ? cypress semiconductor corporation, 2008-2009. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representative s, and distributors. to find t he office closest to you, visit us at www.cypress.com/sales. products psoc psoc.cypress.com clocks & buffers clocks.cypress.com wireless wireless.cypress.com memories memory.cypress.com image sensors image.cyprhess.com [+] feedback |
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